Presently source-coupled logic (SCL) circuits are widely used in mixed mode designs. This is because of several advantages associated with SCL circuits in terms of delay (D), number of transistors (N), current spike (IS) and power-delay-number of transistor-current spike-product (PDNISP) are these have lower values compared to other circuit design techniques. However, the power consumption of SCL circuits is higher. In the present dissertation, various full adder circuits reported in literature have been considered. Properties of the electronic devices change with the variation in process parameters. Process variation is due to variations in the manufacturing conditions such as device dimension, pressure and doping concentration. The variations of various parameters of the full adder circuits with respect to change in process corners has been analysed in the present work. The working of SCL circuits and an SCL circuit minimization technique namely multiplexer minimization technique are studied. Performance of full adder circuits viz. SERF, SERF Imp, PTL, CMOS, SCL, SCL-Min and SCL-Gated has been analysed terms of PDNISP. Power, delay, power delay product, number of transistors, current spike, PDNISP and voltage swing are considered as performance parameters. To study the effect of change in process corners on performance parameters of full adder (FA) circuits, different full adder circuits are analysed in 180nm, 130nm, 90nm and 45nm technology nodes. An SCL full adder (SCL-Gated) and an encoder have been proposed for improved power consumption. From the analysis, it is observed that SCL circuits exhibit low value of IS and PDNISP but at the cost of some other performance parameters such as power and PDP. The performance of proposed FA circuit has been compared with the other SCL FA circuits reported in literature. Power and PDP is significantly reduced in case of SCL-Gated circuit but with slight increase in PDNISP.