16 Bit Microprocessor Architecture Analysis using VHDL


Authors : Kale Swarnita Gorakshanth; Donagre Avinash Sudhakar; Kale Gorakshnath Bhgwatrao

Volume/Issue : Volume 8 - 2023, Issue 1 - January

Google Scholar : https://bit.ly/3IIfn9N

Scribd : https://bit.ly/3kSaVyO

DOI : https://doi.org/10.5281/zenodo.7597005

This paper involves the design and simulation of 16 bit microprocessor architecture on FPGA using VHDL. Significant features such as the , increased speed ,minimal implementation real-estate, reduction in power and maximum configurability are provided by several FPGAs. Where earlier a design may have included 6 to 10 ASICs, but today the same design can be achieved using only single FPGA.VHDL is used in order to programme FPGA.VHDL is very High Speed Integrated Circuit Hardware Description Language. This model actually represents the textual description of a hardware design or a piece of design which, when simulated mimics the design behaviour .The processor contains a number of basic modules. These modules are register array of 8X16 bit register, an ALU, shift register, program counter , an instruction register ,an address register, a comparator and control unit. All of these units or modules are assembled together and communicate through a common 16 bit tristate data bus.

Keywords : Register transfer level, Reduced instruction set computer(RISC), Very high speed integrated circuit(VHSIC) hardware description language , Arithmetic logic unit(ALU), Field programmable gate array(FPGA).

CALL FOR PAPERS


Paper Submission Last Date
31 - March - 2024

Paper Review Notification
In 1-2 Days

Paper Publishing
In 2-3 Days

Video Explanation for Published paper

Never miss an update from Papermashup

Get notified about the latest tutorials and downloads.

Subscribe by Email

Get alerts directly into your inbox after each post and stay updated.
Subscribe
OR

Subscribe by RSS

Add our RSS to your feedreader to get regular updates from us.
Subscribe