A Fault Analysis Perspective of Logic Encryption in Memristor Based Combinational Circuits Using Key Gates


Authors : Dr.K.Paramasivam; N.Nithya

Volume/Issue : Volume 5 - 2020, Issue 6 - June

Google Scholar : http://bitly.ws/9nMw

Scribd : https://bit.ly/31XnYUr

In this paper, a logic locking technique for memristor based combinational circuits using key gates is proposed. The key gates are XOR/XNOR gates with additional inputs referred as keys, which ensures the circuit to provide correct output only for specific input key. The logic encryption with key gates prevents IC’s from camouflaging and overproduction outside foundries. The conventional theories of hardware security, were not concerned about area on chip. In our proposed logic, memristors with very few transistors are used for combinational logic design instead of completely relying on transistor only implementations. The Memristor Ratioed Logic (MRL) is used for designing combinational logic circuits. The SPICE simulations are done using 180um technology with LTSPICE tool and the results shows the total delay of 0.21ns with average power consumption of 647.83μW.

Keywords : Memristor, Linear Ion Drift model, Logic encryption, Key-gates, MRL.

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