In this paper, a logic locking technique for
memristor based combinational circuits using key gates
is proposed. The key gates are XOR/XNOR gates with
additional inputs referred as keys, which ensures the
circuit to provide correct output only for specific input
key. The logic encryption with key gates prevents IC’s
from camouflaging and overproduction outside
foundries. The conventional theories of hardware
security, were not concerned about area on chip. In our
proposed logic, memristors with very few transistors
are used for combinational logic design instead of
completely relying on transistor only implementations.
The Memristor Ratioed Logic (MRL) is used for
designing combinational logic circuits. The SPICE
simulations are done using 180um technology with
LTSPICE tool and the results shows the total delay of
0.21ns with average power consumption of 647.83μW.
Keywords : Memristor, Linear Ion Drift model, Logic encryption, Key-gates, MRL.