A Study on Leakage Power in Flip Flops


Authors : Abdul Aleem Mohammad

Volume/Issue : Volume 2 - 2017, Issue 10 - October

Google Scholar : https://goo.gl/DF9R4u

Scribd : https://goo.gl/V9t7x9

Thomson Reuters ResearcherID : https://goo.gl/3bkzwv

Aggressive scaling of CMOS devices in each technology generation to achieve higher integration density and effective performances has left over so many challenges for designers. The more and more accommodation of components on chip had led to rise in power dissipation as the major challenge. As MOS transistors enter Deep Submicron (DSM) sizes, undesirable consequences regarding power consumption arise. With the smaller geometries in DSM, the number of gates that need to be integrated on a single chip, power density and total power are increasing rapidly. Through this paper, an analytical study on different approaches used to reduce leakage power in sequential circuits especially flip flops has been presented. Continuous efforts have been made by researchers in the recent past to find new techniques in the field of digital sequential circuits to reduce leakage power to obtain a balancing performance among power, delay and area. Much more exploration is needed as the design aspect is concerned.

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