Authors : Meghana M N; Mallikarjuna R Mulimani; Shiva prasad A S; Venkatesh R; Vignesh D

Volume/Issue : Volume 10 - 2025, Issue 5 - May

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Google Scholar : https://tinyurl.com/ccm5pvce

DOI : https://doi.org/10.38124/ijisrt/25may1725

Note : A published paper may take 4-5 working days from the publication date to appear in PlumX Metrics, Semantic Scholar, and ResearchGate.

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Abstract : Booth's Algorithm is a multiplication algorithm used to perform signed binary multiplication efficiently. It minimizes the number of addition and subtraction operations by encoding runs of consecutive ones in the binary representation of a multiplier. This algorithm uses a technique called radix-4 encoding, which reduces the number of required arithmetic operations compared to standard long multiplication. Booth's Algorithm is widely used in computer arithmetic, especially in hardware multipliers, due to its ability to handle both positive and negative numbers uniformly. This paper provides an overview of the algorithm's working mechanism, its advantages, and its significance in digital computing.

Keywords : Booth'sAlgorithm, SignedBinaryMultiplication,Radix-4Encoding,ComputerArithmetic, Hardware Multipliers, Digital Computing, Arithmetic Operations Optimization, Binary Multiplier, Multiplication Algorithm, Run-Length Encoding.

References :

1. Booth, A. D. (1951). “A signed binary multiplication technique.” Quarterly Journal of Mechanics and Applied Mathematics.
2. Wallace, C. S. (1964). “A Suggestion for a Fast Multiplier.” IEEE Transactions on Electronic Computers.
3. Mano, M. M., & Ciletti, M. D. (2017). Digital Design: With an Introduction to the Verilog HDL.
4. Weste, N. H. E., & Harris, D. M. (2010). CMOS VLSI
5. Design: A Circuits and Systems Perspective.
6. Patterson, D. A., & Hennessy, J. L. (2017). Computer Organization and Design RISC-V Edition.
7. Verilog IEEE Standard 1364-2005.
8. Rabaey, J. M. (2003). Digital Integrated Circuits: A Design Perspective.
9. Bhasker, J. (2003). A Verilog HDL Primer.
10. Dandamudi, S. (2005). Fundamentals of Computer Organization and Design.
11. IEEE Xplore digital library research articles on multiplier architectures.