Authors : Akshat Yadav; Gaurav Isame; Parth Sonawane; Satendra Mane

Volume/Issue : Volume 10 - 2025, Issue 5 - May

Google Scholar : https://tinyurl.com/rtnb4nwd

DOI : https://doi.org/10.38124/ijisrt/25may2196

Note : A published paper may take 4-5 working days from the publication date to appear in PlumX Metrics, Semantic Scholar, and ResearchGate.

Abstract : Full adders serve as fundamental building blocks within arithmetic units and digital processing cores. In this paper, the authors present the design and transistor level optimization of a full adder using the static CMOS approach within 90nm technology. Special emphasis is placed on transistor sizing techniques to achieve low power consumption. The authors also compared the design with alternative design methodologies such as Complementary Pass Transistor Logic (CPL) and Transmission Gate Adder (TGA) to establish performance baselines. The final design was simulated and validated in Cadence Virtuoso. The results demonstrate improvements in power and delay, as well as area efficiency suitable for large scale VLSI integration. In addition, the importance of choosing appropriate transistor sizing to manage parasitic capacitance and switching energy is emphasized, ensuring a well optimized and technology compatible design. Furthermore, the comparative study helps to understand trade-offs among different full adder architectures. The results of this research reinforce the relevance of full custom design practices even in modern scaled technologies. This implementation is suited for arithmetic intensive applications in DSP and embedded systems. Its simplicity also enables for easier porting to future process nodes, maintaining design flexibility and reusability.

Keywords : CMOS, Full Adder, Low Power, Transistor Sizing, Cadence Virtuoso.

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