Prashant Singh , Rakesh Jain
Published in: International Journal of Innovative Science and Research Technology
Volume/Issue: Volume 1 Issue 4
Google Scholar: https://goo.gl/adA7TQ
In this paper, we have designed Miller Encoder circuit with the best optimized design of T-flip flop, using 32nm UMC CMOS technology. Different designs of T-Flip Flop has been designed using different techniques like CMOS inverters, HLFF method, NMOS switches, Transmission Gates & GDI (Gate Diffusion Input). Each circuit structure has been designed utilizing 32nanometre UMC CMOS technology as well as compared at 5GHz clock frequency. These designs are simulated in HSPICE software leading to correct behavior up to 5GHz. Best optimized design of T-flip flop is selected and Miller Encoder is formed with the combination of D-flip flop and T-flip flop. Miller Encoder is being widely used in the complex optical communication systems and frequently employed in Radio Frequency Identification Systems (RFID).The crucial advantage of this design is to utilize a clock signal functioning in the similar frequency domain of applied data. Output changes on the rising and falling edges of the clock.
Keywords— RFID, Miller Encoder, Optical Communication System.