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Authors : T Srujana, Dr B Bharathi.

Volume/Issue :-
 Volume 3 Issue 6

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Power consumption has emerged as a main feature of consent in today’s widely used electronic circuits. The consumption of data path is nearly 30% of the total power of high performance microprocessor. The key components used in the data paths are Adders and hence, careful design and analysis is required for these units to obtain optimum performance. In this paper we presented a design for low power, energy efficient full adder circuit by ultra-deep sub- micron technology. The main focus in low power design is targeted to reduce the static power while trading other vital requirements such as driving capability, delay, total power, power delay product and noise. Based on the fact that transmission logic has good driving capability and full signal swing than pass transistor logic, a new full adder cell is proposed to reduce delay and power-delay product (PDP).The simulations have been carried out with TANNER EDA simulation tool using PTM 65nm technology files. The Simulation has been carried out for different supply voltages, loading conditions. The performance of the proposed circuit was compared with respect to the existing ones.
Keywords:- Novel, Low-Power, Energy-Efficient, Full Adder, ultra deep-Submicron.