Fast Address Using Quaternary Signed Digit Number System With Reversible Logic Gate


Authors : Neetu Thomas

Volume/Issue : Volume 1 - 2016, Issue 1 April

Google Scholar : https://goo.gl/RBzpMN

The requirement of a high speed digital circuitry has become a cardinal need as portable multimedia & communication applications that incorporates the process of computing & information processing. The issue related to latest computers has led to degradation in performance of arithmetic functions such as subtraction, addition, division & multiplication on the basis of higher consumption of power, time delay in carry propagation & complicacy in bigger circuitry. The system elaborates the carry free n digits addition/subtraction in the form of carry free propagation which is a necessary factor related to speed of digitized system. In this document, QSD numbers of which radix is 4 are implemented in arithmetic operations for executing carry free arithmetic operations. The QSD numbers ranges in between -3 to 3. In a n-digit QSD number, every digit is presented as digit set of [-3, -2, -1, 0, 1, 2, 3]. In this document, we are working over improvising the performance of QSD addition by implementation of reversible logic gate. QSD addition is implemented for 4-bit. In general circumstances, high delay performance is produced by QSD. We worked over minimizing the delay in 4 bit QSD adder. The pipelining methodology & Peres gate is implemented for minimizing the delay.

Keywords : Carry free addition, Fast computing, FPGA, Quaternary Signed Digit, VHDL, VLSI.

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