The need for high speed digital circuits became more prominent as portable multimedia and communication applications incorporating information processing and computing. The drawback of modern computers lead to the deterioration in performance of arithmetic operations such as addition, subtraction, division, multiplication on the aspects of carry propagation time delay, high power consumption and large circuit complexity. This system explores the carry free n digits addition/subtraction as the carry propagation delay is most important factor regarding the speed of any digital system. In this paper, Quaternary signed digit (QSD) numbers whose radix is 4 are used in arithmetic operations to achieve the carry free arithmetic operations. The range of QSD number is from -3 to 3.In any n digit QSD number ,each digit can be represented by a number from the digit set [-3,-2,-1,0,1,2,3]. In this paper , we are improving the performance of the QSD addition by apply reversible logic gate . QSD addition is performing for the 4 bit,8 bit . In the normal condition QSD adder gives the high delay performance . We have to reduce the delay of the 4 bit,8 bit QSD adder . For reduce the delay we apply pipelining and Peres reversible logic gate . Pipelining and Peres reversible gate will be able to reduce the delay of the 4 bit , 8 bit QSD adder .
Keywords- Carry free addition, Fast computing, FPGA, Quaternary Signed Digit, VHDL, VLSI.