Authors : Ravikumar R; Skanda Gargesh N; Manvith P; Nagarjuna S G; Vanish B H

Volume/Issue : Volume 10 - 2025, Issue 5 - May

Google Scholar : https://tinyurl.com/jzre4ju5

DOI : https://doi.org/10.38124/ijisrt/25may1617

Note : A published paper may take 4-5 working days from the publication date to appear in PlumX Metrics, Semantic Scholar, and ResearchGate.

Abstract : This paper presents the design and performance comparison of different high-speed adder architectures with a focus on optimizing delay, power consumption, and area utilization. A hybrid 128-bit adder is proposed by combining four popular adder types: Ripple Carry Adder (RCA), Carry Skip Adder (CSA), Carry Select Adder (CSLA), and Carry Look- Ahead Adder (CLA). Each adder is allocated to a specific segment of the 128-bit word based on its characteristics to improve overall performance. The design is implemented using SystemVerilog, simulated using Synopsys VCS, and synthesized for FPGA deployment. To enhance performance further, the design incorporates pipelining techniques and is based on NAND gate-level logic for better hardware optimization. Results indicate that the hybrid approach offers an effective trade-off among speed, power, and hardware utilization.

Keywords : Hybrid Adder, System Verilog, RCA, CLA, CSLA, FPGA, High-Speed Arithmetic, Pipelining, NAND Gate.

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