Authors : Kiran P V; Naveen Kumar Kanavi; Gita Reshmi; Veena A

Volume/Issue : Volume 7 - 2022, Issue 2 - February

Google Scholar : http://bitly.ws/gu88

Scribd : https://bit.ly/3tJkFfP

DOI : https://doi.org/10.5281/zenodo.6337837

Abstract : This paper aims to implement a RAM which can address itself to load the data into its memory. Using Xilinx 14.1 ISE for simulation and synthesis the RAM of size 16 x 32 is implemented with consecutive addresses generated automatically by the additional circuit in the design.

Keywords : RAM, BRAM, Single Port BRAM, Dual Port BRAM.