The requirement of A/D converter that is highly-low power, efficient in area & higher in speed is pushed towards implementing in the dynamic comparators that are regenerative type to enhance the efficiency of power & speed. In the last paper , an assessment over delay in the dynamic comparators will be provided & derivations of analytical expressions are performed. From these analytical expressions, designers are able to get an idea regarding major contributors for delay in comparators & perform exploration about tradeoffs completely in design of dynamic comparators. On the basis of provided assessments a latest dynamic comparator is suggested, in which some transformations ar e made to circuitry of traditional double tail comparator for low power & faster operations even when supply voltage is limited. The feedback is strengthened in the regeneration process by not even complicating the structure & invading some more transistors. The outcomes from post simulation help the 0.18-μm CMOS technology to confirm the outcome of the analysis. It is presented from base document that consumption of power & delay are reduced to a great extent in dynamic comparator. In this document we tend to enhance the performance of system by making use of clock gating. As the clock gating is applied, the delay & consumption of power will also get reduced. The suggested system gives the outcome for 1.2V VDD. The length of channel is 130nm. As from the outcomes, it is observed that clock gating helps in minimizing the delay & power in contrast to circuitries presented in previous paper.
Keywords : Index Terms—Clock gating, Double-tail comparator, dynamic clocked comparator, high-speed analog-to-digital converters (ADCs), low-power analog design.