Improve performance of PIPO (Parallel in Parallel Out) Shift Register by use Transistor Gating Technique


Authors : Pradyumna Bhardwaj, Mukesh Maheshwari

Volume/Issue : Volume 2 - 2017, Issue 8 - August

Google Scholar : https://goo.gl/JVeMc5

Scribd : https://goo.gl/kp6Xj9

Thomson Reuters ResearcherID : https://goo.gl/3bkzwv

Shift registers are some sort of sequential logic circuitries that are majorly deployed to store data in digital format. In the previous paper , the implementation of a Four bit Parallel in parallel Out (PIPO) shift Register design are showing by use D Flip Flop. D Flip Flop is designing by use NAND Gate. In this Paper, Improving the performance of the D Flip Flop by use Transistor Gating Technique. As Results Session is showing the power Consumption of the NAND Gate. Power Consumption of NAND gate by use normal CMOS Design is 7.9458*〖10〗^(-11) watts while by use Transistor Gating Technique Power Consumption of NAND Gate gets 1.034*〖10〗^(-08)watts. As use proposed NAND Gate Circuit in the PIPO Circuit the power consumption of the circuit gets 1.34*〖10〗^(-03)watts.

Keywords : Power Gating; Clock Gating; Activity-Driven Optimized Clock-gating; Run Time Power Gating; Serial Input Serial Output Shift Register.

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