Authors :
P. Aruna Priya, K. Chakradhar Reddy, A. Shankar Kalyan, M. S. Chakravarthi
Volume/Issue :
Volume 2 - 2017, Issue 7 - July
Google Scholar :
https://goo.gl/QckhGQ
Scribd :
https://goo.gl/yTesJR
Thomson Reuters ResearcherID :
https://goo.gl/3bkzwv
Abstract :
The main idea is to reduce the power consumption of FIR filter using low power techniques. The Multipliers are heart of the FIR filter which consumes more power, two architectures namely partitioned Multiplier and selective Activation Multiplier are used to achieve low power. Folding technique is used to reduce the number of Multipliers in FIR filter which refers to reduction in power consumption. Power, Delay and Area are calculated using Cadence software. The power reduction is recorded around 34.9% for FIR filter using Partition Multiplier.
Keywords :
Low-Power Multipliers, FIR Filter, Folding Technique.
The main idea is to reduce the power consumption of FIR filter using low power techniques. The Multipliers are heart of the FIR filter which consumes more power, two architectures namely partitioned Multiplier and selective Activation Multiplier are used to achieve low power. Folding technique is used to reduce the number of Multipliers in FIR filter which refers to reduction in power consumption. Power, Delay and Area are calculated using Cadence software. The power reduction is recorded around 34.9% for FIR filter using Partition Multiplier.
Keywords :
Low-Power Multipliers, FIR Filter, Folding Technique.
