Low Delay Based QSD Multiplier

Authors : Pooja Bansal , Vipin kumar Gupta .

Volume/Issue : Volume 1 - 2016, Issue 9 - December

Google Scholar : https://goo.gl/olYMm8

Scribd : https://goo.gl/05sTVc

In this Paper, we are working at 4 bit QSD multiplier. In the QSD multiplier, 4 Bit QSD adder is using. QSD adder contains the addition block which is design by Reversible Logic Gate in proposed design along with pipeline by use Clock Pulse. Proposed QSD adder will use in 4 * 1 multiplier and 4 * 1 multiplier is using in 4 * 4 multiplier. As we can see from the results session, the delay is getting reduce for the proposed QSD 4-bit multiplier. Normally 4 bit, QSD multiplier is showing the delay 49.978 ns while proposed 4 Bit QSD multiplier is giving the delay of 38.919 ns. So from the results session, it is clear that proposed 4-bit QSD multiplier is working fast.

Keywords : Carry free addition, Fast computing, FPGA, Quaternary Signed Digit, VHDL, VLSI.


Paper Submission Last Date
30 - November - 2020

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