Low Power Shift Register Using NAND Gate With 130nm CMOS Design


Authors : Vikas Fageria ,Vipin Gupta

Volume/Issue : Volume 1 - 2016, Issue 3 - June

Google Scholar : https://goo.gl/uHxSRz

Shift registers are some sort of sequential logic circuitries that are majorly deployed to store data in digital format. In the previous paper , the implementation of a Four bit Serial Input Serial Output (SISO) Shift Register using combination of Activity-Driven Optimized Clock-gating (ADOC) scheme and Run Time Power Gating (RTPG). They had proposed Activity-Driven Fine-Grained CG and RTPG integration. First, they introduce an Activity-Driven Optimized Clock-Gating scheme to improve traditional XOR-based CG. It chooses only a subset of Flip-Flops to be gated selectively, then they introduce RTPG which is applied to each and every Flip Flop. The clock enable signal generated by ADOC scheme is used as the sleep signal to all the PG cells. In this paper , we enhance the performance of circuit by designing the XOR gate from support of NAND gate. NAND gate absorbs less power. We proposed a fine-grained CG and RTPG based 4 bit SISO by apply improved XOR gate with NAND logic gate .

Keywords : Power Gating; Clock Gating; Activity-Driven Optimized Clock-gating; Run Time Power Gating; Serial Input Serial Output Shift Register.

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