Authors : Ahmed Salahuddin Suhaib; Dr. M. Asha Rani

Volume/Issue : Volume 10 - 2025, Issue 8 - August

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DOI : https://doi.org/10.38124/ijisrt/25aug1309

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Abstract : The Memory Built-In Self-Test (MBIST) is the standard for testing dense embedded memories that dominate modern SoCs; however, a critical trade-off exists between the test time and fault coverage. While comprehensive algorithms such as March C- (10n) are slow, faster algorithms such as MATS++ (6n) are often preferred, although both aim to detect critical Address Decoder Faults (AFs). This study presents an MBIST controller employing a novel March (5n) algorithm that bridges this gap, offering robust fault coverage with superior efficiency. The core innovation of the algorithm is the "address-as-data" paradigm, which uses the memory address (a) and its bitwise complement (~a) as test patterns to efficiently detect Stuck-at (SAF), Transition (TF), and Address Decoder (AF) faults. The proposed FSM-based controller has been designed in Verilog and validated on a Xilinx Zynq-7000 series FPGA platform. Experimental evaluation demonstrates that the March (5n) algorithm achieves significant reductions in test time compared to established approaches, with minimal resource overhead. These findings highlight the effectiveness of the March (5n) algorithm in achieving a balanced trade-off between speed and fault coverage, positioning it as a practical candidate for deployment in high-volume, cost-sensitive applications.

Keywords : MBIST, March 5n, March C-, MATS++.

References :

1. T. S. Nguan Kong, N. E. Alias, M. L. P. Tan, A. Hamzah, U. U. Sheikh, I. Kamisian, and Y. A. Wahab, "An Efficient March (5n) FSM-Based Memory Built-In Self-Test (MBIST) Architecture," in Proc. 2021 IEEE Regional Symposium on Micro and Nanoelectronics (RSM), 2021, pp. 76-79.
2. B. Singh, A. Khosla, and S. B. Narang, "Area Overhead and Power Analysis of March Algorithms for Memory BIST," Procedia Engineering, vol. 30, pp. 930-936, 2012.
3. M. Parvathi, N. Vasantha, and K. S. Prasad, "Modified March C - Algorithm for Embedded Memory Testing," International Journal of Electrical and Computer Engineering (IJECE), vol. 2, no. 5, pp. 571-576, Oct. 2012.
4. N. Q. M. Noor, Y. Yusof, and A. Saparon, "Low Area FSM-Based Memory BIST for Synchronous SRAM," in Proc. 5th International Colloquium on Signal Processing & Its Applications (CSPA), 2009, pp. 409-412.
5. J. Kruthika, G. R. Nisha, R. Gayathri, and V. Jeyalakshmi, "SRAM Memory Built in Self-Test using MARCH Algorithm," in Proc. 2022 International Conference on Augmented Intelligence and Sustainable Systems (ICAISS), 2022, pp. 1288-1292.
6. L. H. R, Varchaswini R., and Y. J. M. Shirur, "Implementation of FSM-MBIST and Design of Hybrid MBIST for Memory cluster in Asynchronous SoC," International Journal of Computer Applications Technology and Research, vol. 3, no. 4, pp. 216-220, 2014.
7. M. Mamatha and M. Muralidhar, "Memory Testing using March C-Algorithm," International Journal of VLSI System Design and Communication Systems, vol. 2, no. 7, pp. 512-517, Oct. 2014.
8. D. Jariwala and P. Garg, "FSM Based Memory BIST using Verilog-HDL," Dept. of Electronics and Communications Engineering, Nirma University, Ahmedabad, India, 2022.