Authors : Matta Yashwanth Reddy; Dr. G. Sujatha

Volume/Issue : Volume 10 - 2025, Issue 11 - November

Google Scholar : https://tinyurl.com/mpcn3558

Scribd : https://tinyurl.com/bdd6zwkj

DOI : https://doi.org/10.38124/ijisrt/25nov504

Note : A published paper may take 4-5 working days from the publication date to appear in PlumX Metrics, Semantic Scholar, and ResearchGate.

Note : Google Scholar may take 30 to 40 days to display the article.

Abstract : This paper introduces a unique dual-port RAM design that targets both power efficiency and timing performance optimization. The new architecture merges the sophisticated clock gating and the data-transfer pipeline techniques, which make clocks on and off as per the need thus reducing the dynamic power to the most minimum while still using the pipelining technique to its full advantage for throughput and stabilization of timing. In contrast to the classical dual-port RAMs, this design has the simultaneous read and write feature without the energy cost that is traditionally associated with it. The system which is built in Verilog HDL and runs on FPGA platforms overcomes port conflicts by using techniques of port locking and priority management. The results of the tests indicate that there are major savings in power without any degradation in the functional performance, hence this dual-port RAM can be particularly utilized in the applications where efficient parallel memory operation under a strict power constraint is also required. The power-optimized RAM module with robust conflict resolution that is one of the contributions of this work is already showing its potential for high-speed, low-power applications.

Keywords : Dual-Port RAM, FPGA, Verilog HDL, Clock Gating, Pipelining, Concurrent Read/Write, Conflict Resolution.

References :

1. M. R. Reddy, B. A. Reddy, A. Subramanyam, K. S. Reddy, D. R. Reddy, and Y. V. S. Vamsi, "Design and implementation of dual-port RAM with multi-clock support in Verilog," Journal of Computational Analysis and Applications, vol. 33, no. 8, pp. 3835–3842, 2024.
2. A. Abumwais, A. Amirjanov, K. Uygar, and M. Eleyan, "Dual-port content addressable memory for cache memory applications," Computers, Materials & Continua, vol. 70, no. 2, pp. 1571–1587, 2022.
3. M. Jang, "Modular hardware design of pipelined circuits with hazards," ACM Transactions on Embedded Computing Systems, vol. 23, no. 4, pp. 1–23, 2024.
4. A. Arora, M. Kumar, and N. Sharma, "CoMeFa: Compute-in-memory blocks for FPGAs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 10, pp. 1571–1584, 2022.
5. K. Marino, P. Zhang, and V. Prasanna, "ME-ViT: A single-load memory-efficient FPGA accelerator for vision transformers," arXiv preprint arXiv:2402.09709, 2024.
6. N. S. Dhakad and S. K. Vishvakarma, "Configurable multi-port memory architecture for high-speed data communication," arXiv preprint arXiv:2407.20628, 2024.
7. A. Al-Zawawi, K. Erdogan, and V. Kursun, “Low-power clock gating techniques for sequential circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 5, pp. 877–881, May 2012.
8. A. Morgenshtein, I. Cidon, and I. Koren, “Low-power dual-port memory architecture for high-performance SoC,” IEEE Transactions on VLSI Systems, vol. 19, no. 3, pp. 482–492, Mar. 2011.
9. H. Esmaeilzadeh, A. Sampson, L. Ceze, and D. Burger, “Neural acceleration for approximate memory design,” ACM SIGARCH Computer Architecture News, vol. 40, no. 3, pp. 27–38, Jun. 2012.
10. Y. Kim, W. Yang, and O. Mutlu, “Ramulator: A fast and extensible DRAM simulator,” IEEE Computer Architecture Letters, vol. 15, no. 1, pp. 45–49, Jan.–Jun. 2016.
11. Y. Pan, P. Ampadu, and D. Sylvester, “Pipelined error control for low-power and high-speed on-chip interconnects,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 6, pp. 1251–1262, Jun. 2010.
12. J. Abella, P. Chaparro, X. Vera, and A. González, “Low-power and high-performance adaptive memory compression,” IEEE Transactions on Computers, vol. 59, no. 1, pp. 77–90, Jan. 2010.