Padding Of LFSR Seeds with Low Transition Bits for Reduced Input Test Data Volume


Authors : Aiswarya Vijayan P; Sajitha A S

Volume/Issue : Volume 7 - 2022, Issue 7 - July

Google Scholar : https://bit.ly/3IIfn9N

Scribd : https://bit.ly/3OgijgF

DOI : https://doi.org/10.5281/zenodo.6866990

Abstract : In testing there are two primary domains one is reducing input test data volume and next is reducing the test power consumption. Commonly used test compression method is on-chip decompression logic based on LFSR and compressed test consist of seeds for LFSR. The padding of LFSR seeds is a method to generate higher bits of LFSR by adding extra bits to an existing seed and random test patterns can be generated. Further using modified dual CLCG more randomization is possible and it increases the fault coverage. By using bit swapping LFSR it is possible to reduce the number of transitions that occurs in a scan chain. Bit swapping lfsr is used to produce seeds for modified dual CLCG. Thus the overall switching activities can be reduced which automatically reduce the power consumption. The primary aim is to reduce the test pattern and to increase the fault coverage with low transition bits

Keywords : bit swapping linear feedback shift register, modified dual CLCG.

In testing there are two primary domains one is reducing input test data volume and next is reducing the test power consumption. Commonly used test compression method is on-chip decompression logic based on LFSR and compressed test consist of seeds for LFSR. The padding of LFSR seeds is a method to generate higher bits of LFSR by adding extra bits to an existing seed and random test patterns can be generated. Further using modified dual CLCG more randomization is possible and it increases the fault coverage. By using bit swapping LFSR it is possible to reduce the number of transitions that occurs in a scan chain. Bit swapping lfsr is used to produce seeds for modified dual CLCG. Thus the overall switching activities can be reduced which automatically reduce the power consumption. The primary aim is to reduce the test pattern and to increase the fault coverage with low transition bits

Keywords : bit swapping linear feedback shift register, modified dual CLCG.

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