Performance Analysis of Reconfigurable Multiplier Unit for FIR Filter Design

Authors : Jalaja S; Pooja M.V

Volume/Issue : Volume 8 - 2023, Issue 7 - July

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The design of Finite Impulse Response (FIR) filter performance is analyzed using Reconfigurable multipliers unit (Dadda, Booth, Wallace, and Shift & Add multipliers) and retimed SQRT CSLA block. The FIR filter is frequently used in digital signal processing technique for a variety of applications including speech processing, loudspeaker equalization, echo cancellation, noise cancellation, arithmetic computations, and image processing. In this paper, the FIR filter takes an input channel and produces multiple output channels by multiplying the input samples with corresponding filter coefficients. The reconfigurable nature of the filter allows for flexibility in selecting the type of multiplier based on specific performance requirements or resource constraints. The specific architecture and interconnections of the components, such as multipliers, adders, and output channels, depend on the chosen multiplier type and the desired property of the filter. The nature of the Control signals is to switch between different multiplier types and adjust the filter accordingly. To optimize the utilization of resources, a resource sharing principle is employed in the proposed FIR filter architecture, regardless of the number of channels and taps. These techniques ensure efficient resource allocation and utilization. The FIR architecture is restructured by incorporating adders and different multipliers in this design. This approach effectively reduces the area occupied by the adders and multiplier blocks, resulting in improved area efficiency and delay. The structure of the FIR filter has the multipliers arranged in a Multiply-Accumulate (MAC) structure, where the multiplication and accumulation operations are performed, and the delay blocks serve as the major building blocks of the filter. The speed of the multiplier is one the component of FIR filter performance, as it determines the critical path in the filter structure. As a result, the proposed architecture power consumption is less compared to existing method [18][19][20][21]. The modified FIR filter coding is implemented using, Verilog Hardware Description Language (HDL). The simulation and synthesis processes are carried out which allows for testing and optimization of the design. The paper introduces a novel approach low power Reconfigurable multiplier unit to design Finite Impulse Response architecture and it shows better efficiency compared to existing architecture [9].

Keywords : Reconfigurable Multiplier, FIR Filter, Dadda, Booth, Wallace, and Shift & Add Multipliers, Resource Sharing Principle, Retime SQRT CSLA.


Paper Submission Last Date
31 - December - 2023

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