Study of Performance of Dynamic Carry Skip Adder using 22nm Strained Silicon CMOS Technology


Authors : E. Hemalatha, D. Anisha Esther Annabai , C. Divya , J. Ajayan

Volume/Issue : Volume 3 - 2018, Issue 1 - January

Google Scholar : https://goo.gl/DF9R4u

Scribd : https://goo.gl/dLG3ZH

Thomson Reuters ResearcherID : https://goo.gl/3bkzwv

Adders are surveyed based on their delay, power and area. Most of the research in the last few years have concentrated on reducing the delay of adders and also power consumption. Carry skip adders are widely used in tree structure configuration for high speed performance. This paper analysis on speed, delay, area and temperature effect of 256 bit carry skip adder using 22nm strained silicon CMOS technology and it uses a supply voltage 0.8V. The simulation results are obtained by a HSPICE software tool. This dynamic carry skip adders consumes only 50% area compared to static CMOS technology based carry skip adders and also speed of the circuit will be increased.

Keywords : Carry Skip Adder, High Speed Performance, Power Consumption, and CMOS Technology Etc…

CALL FOR PAPERS


Paper Submission Last Date
30 - September - 2021

Paper Review Notification
In 1-2 Days

Paper Publishing
In 2-3 Days

Never miss an update from Papermashup

Get notified about the latest tutorials and downloads.

Subscribe by Email

Get alerts directly into your inbox after each post and stay updated.
Subscribe
OR

Subscribe by RSS

Add our RSS to your feedreader to get regular updates from us.
Subscribe