Authors : Subhadip Ghanta; Sanket Shaw; Abdul Barish Khan; Debjyoti Sarkar; Soumik Das

Volume/Issue : Volume 11 - 2026, Issue 3 - March

Google Scholar : https://tinyurl.com/fa6eff2h

Scribd : https://tinyurl.com/4f6tp945

DOI : https://doi.org/10.38124/ijisrt/26mar690

Note : A published paper may take 4-5 working days from the publication date to appear in PlumX Metrics, Semantic Scholar, and ResearchGate.

Abstract : Multiply-Accumulate units are basic components of digital signal processing systems as well as embedded systems, where computational throughput as well as power constraints are of great importance. In this paper, a Power Performance Area trade-off of Vedic Multiplier-based Multiply-Accumulate units with five different adder styles, namely Ripple-Carry Adder, Carry-Skip Adder, Carry-Look-Ahead Adder, Brent-Kung Adder, and Kogge-Stone Adder, is presented. In this paper, a novel Multiply-Accumulate architecture based on a hierarchical 16×16 Vedic Multiplier with a 32-bit accumulation path is presented, which has been implemented on a Zynq-7000 FPGA platform based on the Zed Board platform. The architectures are tested with both 16-bit and 32-bit datapath configurations in terms of power consumption, propagation delay, Power Delay Product, as well as Energy Delay Product, along with hardware utilization. The experimental results show that the Kogge-Stone Adder-based Multiply Accumulate architecture has the least propagation delay of 3.2 ns as well as 5.2 ns for 16-bit as well as 32-bit datapath configurations, respectively, achieving the least PDP of 304 pJ as well as 728 pJ, respectively, compared to other adder styles. In contrast, the Ripple Carry Adder consumes the least power of 40 mW as well as 83 mW for 16-bit and 32-bit datapath configurations, respectively, utilizing the least hardware resources, but has the highest propagation delay of 12.5 ns and 21 ns, respectively. Among all architectures, the Brent-Kung Adder offers the best trade-off among power, delay, and hardware utilization. The adderbased Multiply-Accumulate architectures are suitable for implementing various high-performance as well as powerefficient applications, including digital signal processing, image processing, and machine learning accelerators.

Keywords : Multiply–Accumulate (MAC), Vedic Multiplier, Adder, Power–Performance–Area (PPA), Zynq-7000 FPGA.

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