Authors : Singala Sowmya; C. H. Pallavi

Volume/Issue : Volume 11 - 2026, Issue 7 - July

Google Scholar : https://tinyurl.com/svw769e5

Scribd : https://tinyurl.com/ywvx6fzs

DOI : https://doi.org/10.38124/ijisrt/26jul539

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Abstract : Deep-submicron VLSI testing has grown increasingly complex, costly, and power-intensive, motivating on-chip test solutions that do not depend on expensive external automatic test equipment. This work presents a Verilog-based BuiltIn Self-Test (BIST) architecture built around a Linear Feedback Shift Register (LFSR) test pattern generator and a Multiple Input Signature Register (MISR) output response analyzer, targeted specifically at low-power VLSI circuits. The Circuit Under Test (CUT) is realized as an N×N multiplier, a component whose correct operation is critical to the reliability of digital signal processing and arithmetic datapaths. The LFSR generates pseudo-random test vectors with reduced switching activity, while the MISR compresses the CUT's output responses into a compact signature that is compared against a knowngood value, avoiding the need to store or stream full response vectors off-chip. Power-aware techniques, including reduced test-vector transitions and clock gating on idle test logic, are applied to keep dynamic power during test mode close to functional-mode levels. The complete LFSR–MISR BIST datapath and the N×N multiplier CUT are described and verified in Verilog, synthesized for a low-power target, and evaluated through gate-level simulation. Simulation results confirm that the proposed LFSR–MISR BIST architecture achieves high fault coverage with substantially lower power consumption than conventional external test methods, while adding only modest area overhead and leaving the multiplier's functional performance unaffected, making the approach attractive for both high-performance and battery-powered VLSI applications.

Keywords : BIST, LFSR, MISR, Test Pattern Generator, Signature Analysis, Low-Power Testing, VLSI, Verilog.

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