Wireless Sensor Network of 3 – Bit ADC


Authors : B. Sujitha

Volume/Issue : Volume 4 - 2019, Issue 7 - July

Google Scholar : https://goo.gl/DF9R4u

Scribd : https://bit.ly/2Tszn88

Abstract : More recent attention is focused on smart dust or on wireless sensor networks. Sensor and process-type, autonomous, very low-powered electronic devices transmit data from one node (mote) to another in an ad-hoc network by transmitting the environment variations. The smart dust subsystems generally include analog (AI) interface, analog-to-digital (ADC), digital signal processor (DSP), digital-to-analog (DAC), and power management and communication transceiver. A clock less EDADC system is presented using the technique of CT delta modulation (DM). The ADC output is digital, time-controlled, data token. The ADC uses a DAC feedback, which is area efficient and segmented resistor string. There is a study of various R-string DAC architectures. A comparison of a component reduction to a prior art indicates that the DAC and D flip-flops in 8-bit ADC bidirectional register have reduced resistors and switches by nearly 87.5 percent using the proposed segmented DAC architecture. SNDR is 22.696 dB, 30,435 dB and 55.73 dB respectively, for the 3-bit, 4-bit and 8-bit systems, and interest ranges are as high as 220.5 kHz.

Keywords : Event-Driven (ED), Continuous Time (CT), Delta-Modulation (DM), Digital Signal Processing (DSP).

More recent attention is focused on smart dust or on wireless sensor networks. Sensor and process-type, autonomous, very low-powered electronic devices transmit data from one node (mote) to another in an ad-hoc network by transmitting the environment variations. The smart dust subsystems generally include analog (AI) interface, analog-to-digital (ADC), digital signal processor (DSP), digital-to-analog (DAC), and power management and communication transceiver. A clock less EDADC system is presented using the technique of CT delta modulation (DM). The ADC output is digital, time-controlled, data token. The ADC uses a DAC feedback, which is area efficient and segmented resistor string. There is a study of various R-string DAC architectures. A comparison of a component reduction to a prior art indicates that the DAC and D flip-flops in 8-bit ADC bidirectional register have reduced resistors and switches by nearly 87.5 percent using the proposed segmented DAC architecture. SNDR is 22.696 dB, 30,435 dB and 55.73 dB respectively, for the 3-bit, 4-bit and 8-bit systems, and interest ranges are as high as 220.5 kHz.

Keywords : Event-Driven (ED), Continuous Time (CT), Delta-Modulation (DM), Digital Signal Processing (DSP).

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