Low power and area proficient high-speed
circuits are the most important areas in VLSI design
research. Carry select adder is one of the fastest adders
with the low area and power consumption. The paper
introduces a 16-bit carry select adder with an optimized
multiplexer based full adder circuit using Gate
Diffusion Input logic (GDI) technology. Comparison is
done on Area, Power and Delay parameters. Our circuit
requires only two XOR gates and a multiplexer. In this,
each logic gate is designed using GDI technology. This
further reduces the transistor count resulting in Area,
power, delay and complexity minimization. The
proposed 16-bit carry select adder provides better
results compared to the conventional 16-bit carry select
adder with Area and delay.
Keywords : Optimized multiplexer-based adder, carry select adder, GDI technology.