Authors : Shalini Priya; Ashish Dubey

Volume/Issue : Volume 10 - 2025, Issue 7 - July

Google Scholar : https://tinyurl.com/3zdexb3b

Scribd : https://tinyurl.com/rwvhmthu

DOI : https://doi.org/10.38124/ijisrt/25jul651

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Abstract : This paper presents a parameterised FIFO architecture optimized for eliminat- ing idle bubble cycles in GPU data pipelines. The design focuses on addressing classical inefficiencies in FIFO-based data transfers, especially under boundary conditions such as full and empty queue states. The proposed architecture en- sures concurrent read and write transactions without causing data corruption or latency penalties. The FIFO logic was implemented using synthesizer-portable SystemVerilog and verified using a Universal Verification Methodology (UVM) testbench. The design achieves 100% functional coverage across over 10 million simulation transactions. ASIC synthesis was carried out using a 28 nm low-power CMOS process, and the results show a 12% reduction in silicon area and 18% savings in dynamic power compared to traditional synchronous FIFO IPs. The architecture is scalable in both depth and width, and it can be inte- grated directly into high-performance GPU shader pipelines. This work offers a viable solution for improving data-path efficiency in compute-intensive system- on-chip (SoC) designs.

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