Authors : Santosh Krishnakant Rai; Chandrahas Sahu

Volume/Issue : Volume 9 - 2024, Issue 9 - September

Google Scholar : https://tinyurl.com/4hjekstn

Scribd : https://tinyurl.com/h6ks679x

DOI : https://doi.org/10.38124/ijisrt/IJISRT24SEP1230

Note : A published paper may take 4-5 working days from the publication date to appear in PlumX Metrics, Semantic Scholar, and ResearchGate.

Abstract : In order to lower power consumption and leakage currents during active operation, the suggested SRAM architecture with power gating design trims the source voltage across the SRAM cell, ranging from 50 to 150 mV. Power gating based on sectors is utilized, using a self-biasing approach where the gate terminal and source of a PMOS transistor act as a diode, controlling the virtual ground. However, three challenges arise with this method in nanometer technology: the additional self- biasing transistor (SBT) occupies 5% more space, the source voltage adjustment mechanisms are not effectively implemented, and the increase in virtual ground voltage leads to bias temperature instability. To implement this design, a 4x4 SRAM cell array is constructed, consisting of 4 rows and 4 columns of 10T SRAM cells. A decoder addresses these cells, and each row represents half a byte, with control circuitry managing input and output data. Additionally, the outputs of individual cells in each column are combined using a 4-bit OR, producing a single data output point. This architecture effectively reduces power consumption while maintaining operational efficiency, making it suitable for nanometer-scale SRAM designs.

Keywords : Schmitt Trigger Inverter, Stacked Transistor, SRAM and Power Gating.

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