Authors :
Dr. Akhil Masurkar; Hithesh Nagula
Volume/Issue :
Volume 11 - 2026, Issue 5 - May
Google Scholar :
https://tinyurl.com/mvzjph2e
Scribd :
https://tinyurl.com/y2pu32cb
DOI :
https://doi.org/10.38124/ijisrt/26May175
Note : A published paper may take 4-5 working days from the publication date to appear in PlumX Metrics, Semantic Scholar, and ResearchGate.
Abstract :
Digital-to-Analog Converters(DACs) play a vital role in modern mixed-signal systems by transforming digital data
into precise analog outputs. This research presents a comparative analysis of two prominent DAC architectures—R– 2R
Ladder and Current Steering DAC—implemented in Cadence Virtuoso using 180nm CMOS technology for 3-bit and 5-bit
resolutions. The study focuses on evaluating linearity parameters such as Differential Non-Linearity (DNL) and Integral
Non-Linearity (INL), along with performance metrics including speed, design complexity, and application suitability.
Simulation results obtained using the Spectre simulator confirm accurate and monotonic digital-to-analog conversion for
both architectures. The R–2R Ladder DAC demonstrates excellent simplicity and power efficiency, making it ideal for lowto medium-speed applications. Conversely, the Current Steering DAC exhibits superior linearity, faster response, and
minimal glitch energy, proving advantageous for high-speed and high- frequency systems. The comparative findings
highlight the trade-offs between ease of implementation and performance precision, offering insights into selecting
appropriate DAC architectures for specific mixed-signal design requirements. This study validates the effectiveness of both
designs and establishes a framework for optimizing DAC performance in future CMOS-based integrated circuit
applications.
Keywords :
R–2R Ladder DAC, Current Steering DAC, Cadence Virtuoso, INL, DNL, 3-bit, 5-bit.
References :
- B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., New York: McGraw-Hill Education, 2016.
- R. J. Baker, CMOS: Circuit Design, Layout, and Simulation, 4th ed., Hoboken, NJ: John Wiley & Sons, 2019.
- A. S. Sedra and K. C. Smith, Microelectronic Circuits, 8th ed., Oxford University Press, 2020.
- “R–2R Ladder Digital to Analog Converter – Working and Applications,” Electronics Tutorials, [Online]. Available: https://www.electronics-tutorials.ws/
- “Current Steering DACs – Architecture and Analysis,” Analog Devices, [Online]. Available: https://www.analog.com/en/
- Cadence Design Systems, Virtuoso Spectre Circuit Simulator User Guide, Version 20.1, 2023.
- Texas Instruments, “Understanding Data Converters,” Application Report, 2022.
- S. R. Natarajan and A. Chatterjee, “Design and Analysis of High-Speed Current-Steering DAC for Mixed-Signal Applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 4, pp. 1558–1568, Apr. 2022.
- J. Li, K. Chen, and Z. Wang, “A Low-Power R–2R Ladder DAC for Sensor Interface Systems,” IEEE Access, vol. 11, pp. 51342–51349, 2023.
- P. Malcovati, F. Maloberti, and A. Baschirotto, “High- Resolution DAC Architectures for Data Conversion in CMOS Technologies,” IEEE Journal of Solid-State Circuits, vol. 56, no. 3, pp. 723–734, Mar. 2021.
- M. Alioto and G. Palumbo, “Modeling and Design of CMOS Current-Steering DACs with Finite Output Resistance,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 2, pp. 671–675, Feb. 2021.
- A. Sharma, “Comparative Study of R–2R Ladder and Current Steering DAC Architectures using 180 nm CMOS Technology,” International Journal of Electronics and Communication Engineering, vol. 14, no. 7, pp. 255–260, Jul.2020.
Digital-to-Analog Converters(DACs) play a vital role in modern mixed-signal systems by transforming digital data
into precise analog outputs. This research presents a comparative analysis of two prominent DAC architectures—R– 2R
Ladder and Current Steering DAC—implemented in Cadence Virtuoso using 180nm CMOS technology for 3-bit and 5-bit
resolutions. The study focuses on evaluating linearity parameters such as Differential Non-Linearity (DNL) and Integral
Non-Linearity (INL), along with performance metrics including speed, design complexity, and application suitability.
Simulation results obtained using the Spectre simulator confirm accurate and monotonic digital-to-analog conversion for
both architectures. The R–2R Ladder DAC demonstrates excellent simplicity and power efficiency, making it ideal for lowto medium-speed applications. Conversely, the Current Steering DAC exhibits superior linearity, faster response, and
minimal glitch energy, proving advantageous for high-speed and high- frequency systems. The comparative findings
highlight the trade-offs between ease of implementation and performance precision, offering insights into selecting
appropriate DAC architectures for specific mixed-signal design requirements. This study validates the effectiveness of both
designs and establishes a framework for optimizing DAC performance in future CMOS-based integrated circuit
applications.
Keywords :
R–2R Ladder DAC, Current Steering DAC, Cadence Virtuoso, INL, DNL, 3-bit, 5-bit.