The paper deals with the effort to design dataflow computer architecture generator that is capable to generate dataflow computer architectures in the form of the hardware description in VHDL source code that can be implemented in Xilinx FPGA chip. In this work textual form of the dataflow graph is designed along with the generator which translates this dataflow graph into the description of the computer hardware in VHDL language.

Keywords : Dataflow architecture, dataflow graph, VHDL, FPGA, Xilinx.