In this project, the aim is to protect the circuit from transient errors due to increase in rate of transient errors in logic circuits. This is done by designing a transient secure encoder and decoder using Verilog HDL. Project is divided into two parts. First is errordetection module, which is used to detect error in the encoder circuit. if there is any error in the code word the encoder circuit does not allow the code word to pass further. RE-DO operation takes place and the new input is taken for the code word to pass through encoder circuit. Second part is the majority logic decoding in which corrector is used to correct the codes if there is any transient generated during decoding the code word. The result demonstrate that the method is effective for EG-LDPC codes which are one step majority logic decodable. This proposed method has reduced decoding time by detecting whether the code word has error in the first iteration of majority logic decoding and if the code is error free the decoding stops without completing the rest of the iterations. In this way decoding time will greatly be reduced. The design is implemented in board and performed coding in Verilog hardware description language and simulating in Xilinx ISE Simulator.
Keywords : Verilog HDL, EG-LDPC codes, majority logic decoding, Xilinx ISE simulator.