Authors : M. Venkatasai Ashwinmitra

Volume/Issue : Volume 11 - 2026, Issue 6 - June

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Google Scholar : https://tinyurl.com/4fd9hsxj

Scribd : https://tinyurl.com/ybncj8dr

DOI : https://doi.org/10.38124/ijisrt/26jun2006

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Abstract : This paper presents the design and implementation of a Low power and efficient Flash ADC. Several comparators and encoders were developed (AND/OR/XNOR/NOT, XOR, NAND/NOR, and inverter-based), integrated into full Flash ADCs, and their dynamic power, static power, and propagation delay measured A Flash ADC uses a parallel comparator network and a priority encoder for conversion of analog to signals into a digital output. This is achieved in a single clock cycle. In this work, both 3-bit and 4-bit Flash ADCs has been implemented in Vivado using different logic gate combinations to evaluate performance metrics such as dynamic power, static power, and propagation delay. The Flash ADC using NAND-NOR gates encoder and an inverter has used the least power in both 3-bit and 4-bit

Keywords : Flash ADC, Comparator, Encoder, Verilog, Power Analysis, Dynamic Power, Static Power, Delay.

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