Authors :
Gurmeet Kaur Arora
Volume/Issue :
Volume 8 - 2023, Issue 5 - May
Google Scholar :
https://bit.ly/3TmGbDi
Scribd :
https://shorturl.at/DHKV1
DOI :
https://doi.org/10.5281/zenodo.8099424
Abstract :
General-Purpose Processors (GPP)-based
computers and Application Specific Integrated Circuits
(ASICs) are the typical computing platforms used to
develop the back propagation (BP) algorithm-based
Artificial Neural Network (ANN) systems, but these
computing devices constitute a hurdle for further
advanced improvements due to a high requirement for
sustaining a balance between performance and
flexibility. In this work, architecture for BP learning
algorithm using a 16-bit fixed- point representation is
designed for the classification of handwritten digits on a
field- programmable gate array (FPGA). The proposed
design is directly coded and optimized for resource
utilization and frequency in Verilog Hardware
Description Language (HDL) and synthesized on the
ML-605 Virtex 6 evaluation board. Experimental results
show 10 times speedup and reduced hardware utilization
when compared with existing implementations from
literature. The architecture is expandable to other
specifications in terms of number of layers, number of
neurons in each layer, and the activation function for
each neuron. The correctness of the proposed design is
authenticated by comparing parameters obtained
through Python code and Verilog.
Keywords :
General purpose processors (GPP), application specific integrated circuits (ASICs), artificial neural network (ANN), resource utilization, hardware descriptive language (HDL), field programmable gatearray (FPGA).
General-Purpose Processors (GPP)-based
computers and Application Specific Integrated Circuits
(ASICs) are the typical computing platforms used to
develop the back propagation (BP) algorithm-based
Artificial Neural Network (ANN) systems, but these
computing devices constitute a hurdle for further
advanced improvements due to a high requirement for
sustaining a balance between performance and
flexibility. In this work, architecture for BP learning
algorithm using a 16-bit fixed- point representation is
designed for the classification of handwritten digits on a
field- programmable gate array (FPGA). The proposed
design is directly coded and optimized for resource
utilization and frequency in Verilog Hardware
Description Language (HDL) and synthesized on the
ML-605 Virtex 6 evaluation board. Experimental results
show 10 times speedup and reduced hardware utilization
when compared with existing implementations from
literature. The architecture is expandable to other
specifications in terms of number of layers, number of
neurons in each layer, and the activation function for
each neuron. The correctness of the proposed design is
authenticated by comparing parameters obtained
through Python code and Verilog.
Keywords :
General purpose processors (GPP), application specific integrated circuits (ASICs), artificial neural network (ANN), resource utilization, hardware descriptive language (HDL), field programmable gatearray (FPGA).
