Authors : Kalluri Bhavana; T. Satya Savithri

Volume/Issue : Volume 10 - 2025, Issue 11 - November

Google Scholar : https://tinyurl.com/455hjmes

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DOI : https://doi.org/10.38124/ijisrt/25nov569

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Abstract : This paper presents the design of a Fixed-point Kalman Filter Bank Architecture and its implementation on the PYNQ-Z2 FPGA. The proposed architecture comprises Q1.15 fixed-point arithmetic, saturation logic and reciprocal-based safe division, which are utilized to ensure numerical stability and hardware efficiency. Initially, the architecture for a single filter is designed and simulated for a sinusoidal input, and then replicated 8 times to create a single Kalman filter bank module with a span of angular frequencies from 0.001 to 0.029 rad/sample. The constructed Kalman filter bank is created as an IP and implemented on the PYNQ Z2 FPGA board. The design communicates via AXI4-DMA interface between the Processing System (PS) and Programmable Logic (PL). Experimental results demonstrate effective denoising of sinusoidal signals under varying noise levels- low, medium and high noise. The obtained results show an average RMSE below 0.15 and a correlation coefficient above 0.95. Post place-and-route results on the device indicate a resource utilization of 37,596 LUTs (70.67%), 124 DSP slices (56.36%), and 2BRAMs (1.79%), with a maximum operating frequency of 21.4 MHz and total power consumption of 1.48 W.

Keywords : Kalman Filter, Fixed-Point Arithmetic, FPGA, PYNQ-Z2, Filter Bank, AXI4-Stream, Signal Denoising, Q1.15.

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