Authors : Dr. J. Kamala; M. V. Tejendra Prasad

Volume/Issue : Volume 9 - 2024, Issue 5 - May

Google Scholar : https://tinyurl.com/c9tdvsax

Scribd : https://tinyurl.com/3fvzkdnx

DOI : https://doi.org/10.38124/ijisrt/IJISRT24MAY261

Abstract : A 13-bit multiplier is implemented on the Artix- 7 100T FPGA using a divide-and-conquer algorithm. The designis coded in SystemVerilog, leveraging its powerful features for hardware description and synthesis. The divide-and-conquer approach breaks down the multiplication task into smaller sub- tasks, enhancing efficiency and reducing complexity. The FPGA’s high- performance capabilities, particularly on the Artix-7 100T board, make it well-suited for accelerating the computations involved. Additionally, Area Delay Product (ADP) tools are employed to evaluate the algorithm’s efficiency. This project aims to showcase the synergy between algorithmic design, hardware implementation, and FPGA capabilities, emphasizing the versa- tility of the Artix-7 100T FPGA in handling complex arithmetic operations.

Keywords : Multiplier, Verilog, FPGA, Areadelayprod- UCT(ADP).

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