Implementation of High Speed Vedic Multiplier


Authors : M.Durga Madhuri, G.Sweta Sree,D.Raghunadh,G.Panduranga Vittal, Ch.Surya Narayana.

Volume/Issue : Volume 2 - 2017, Issue 3 - March

Google Scholar : https://goo.gl/ukIAJb

Scribd : https://goo.gl/XPSL1Z

Thomson Reuters ResearcherID : https://goo.gl/3bkzwv

Today processor needs high speed multipliers.Multipliers are the essential block to process functions in high speed arithmetic logic units, multiplier and accumulate units, digital signal processing units etc. To enhance speed many modifications over the standard modified booth algorithm, Wallace tree methods for multiplier design have been made and several new techniques are being worked upon. With the increasing constraints on delay, more and more emphasis is being laid on design of faster multiplications. Among these Vedic multipliers based on Vedic mathematics are presently focused due to these being one of the fastest and low power multiplier. Out of sixteen sutras in Vedic mathematics of multiplication “Urdhva Tiryagbhyam” has been selected as a most efficient one in terms of speed. A large number of high speed Vedic multipliers have been proposed with Urdhva Tiryagbhyam sutra. Few of them are presented in this paper giving an insight into their methodology, merits and demerits. Carry save adder, Ripple carry adder based Vedic Multipliers show considerable improvements in speed and area efficiency over the conventional ones.

Keywords : Vedic mathematics, Urdhva Tiryagbhyam, carry save adder, ripple carry adder.

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