Reduce Power Consumption and Area of JK and SR Flip Flop by use Gate Diffusion Input

Authors : Ankit Fogat, Lokesh Lodha.

Volume/Issue : Volume 2 - 2017, Issue 6 - June

This article is presenting a very fast, minimum power simultaneously timed NOR / NAND gate founded JK flip-flop by adjusted Gate Diffusion Input or GDI process in 130 nm technology. We introduce two kinds of flip-flop, NAND gate founded and NOR gate founded. We encounter the two kinds of problems; firstly, the significant power usage, and secondly, the great quantities of transistor using power. To additionally improve the implementation of the JK flip flop, we utilize the Modified Gate Diffusion Input or M-GDI method. In this case, a reduced quantity of transistors will be employed, and the power usage will additionally be less. M-GDI is a method for reduced power conjunctional computerized circuit where logic gates are devised by utilizing reduced quantity of transistor. This method allows the lowering of the power usage, diffusion setback, and surface of the circuits having minimum intricacy of logic model.

Keywords : Modified Gate Diffusion Input (GDI) procedure, low power, high speed, power delay product (PDP), transistor count, area.


Paper Submission Last Date
31 - December - 2022

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