Simulation & Analysis of 10-Stage Delay Line using CNT Transistor at 32nm


Authors : Vikash Sharma, Ambarish Singh Tomar, Nikhil Saxena.

Volume/Issue : Volume 3 - 2018, Issue 6 - June

Google Scholar : https://goo.gl/DF9R4u

Scribd : https://goo.gl/wQqnHF

Thomson Reuters ResearcherID : https://goo.gl/3bkzwv

In this article the equivalent study of discrete parameters of delay line by using CMOS and CNT techniquesare done. After the comparative study the results exhibited that the CNT displayed better results as compared to the CMOS 10 stages delay line at 32nm technology design. Two parameters propagation delay and average power consumption are also calculated andcompared. After the comparison of parameters it is found that CNT delay line has better results as compared to CMOS delay line. The power consumption is also decreased in the Delay line by using CNT as compared to CMOS delay line. During simulation it is found that the propagation delay of CNT delay line reduced by 4.06% then CMOS delay line. Similarly it is also measured during simulation that avg. power consumption of CNT delay line reduced by 20.99% as compared to CMOS delay line. However Voltage using during both type of material is similar and fixed at 0.9v.

Keywords : Carbon nanotube, CMOS, Delay line, Power consumption, Propagation delay etc.

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