Authors : Falodun Olugbenga Abiola; Aloba Tosin Oluwagbenga; Ayileka Ojo Samson

Volume/Issue : Volume 9 - 2024, Issue 8 - August

Google Scholar : https://tinyurl.com/hpm8ce83

Scribd : https://tinyurl.com/2skyy5rj

DOI : https://doi.org/10.38124/ijisrt/IJISRT24AUG608

Note : A published paper may take 4-5 working days from the publication date to appear in PlumX Metrics, Semantic Scholar, and ResearchGate.

Abstract : Accurate simulation of digital logic circuits is essential for ensuring their functionality before actual hardware implementation. The performance of the Digital Electronic Educational Design System (DEEDS) simulator was evaluated by applying it to half adder and full adder logic circuits. The goal is to assess the precision and dependability of DEEDS by comparing its simulation outcomes with theoretical expectations for these fundamental arithmetic components. This study employs DEEDS to model and simulate these adder circuits, with a focus on comparing the simulation results to theoretical predictions. The verification process involves a thorough examination of the sum and carry outputs for both half adder and full adder circuits across various input scenarios. The analysis identifies any discrepancies between the simulated and theoretical results and explores potential sources of these discrepancies. The results demonstrate that DEEDS offers a reliable and accurate simulation platform for these essential digital circuits, with simulated results closely matching theoretical expectations. This verification highlights DEEDS' effectiveness as a tool for digital circuit design and analysis.

Keywords : Digital Electronics Education And Design Suiter Simulator (DEEDS), Half Adder, Full Adder, Karnaugh Maps.

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